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Write assist negative bit line voltage generator for SRAM array
Write assist negative bit line voltage generator for SRAM array
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机译:用于SRAM阵列的写辅助负位线电压发生器
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摘要
A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.
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