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METHOD AND SYSTEM FOR REGISTERING CIRCUIT DESIGN LAYOUT AND SCANNING ELECTRON MICROSCOPE IMAGE, CIRCUIT DESIGN LAYOUT AND IMAGING ERROR CALCULATION METHOD THEREOF, AND ELECTRONIC DEVICE
METHOD AND SYSTEM FOR REGISTERING CIRCUIT DESIGN LAYOUT AND SCANNING ELECTRON MICROSCOPE IMAGE, CIRCUIT DESIGN LAYOUT AND IMAGING ERROR CALCULATION METHOD THEREOF, AND ELECTRONIC DEVICE
The present invention provides a method for registering a circuit design layout and a scanning electron microscope image. The method comprises: step S1, providing a circuit design layout and a scanning electron microscope image to be registered; step S2, processing the circuit design layout to acquire a binary design layout image, and processing the scanning electron microscope image to acquire a binary scanning electron microscope image; step S3, performing Gaussian filtering on the binary design layout image and the binary scanning electron microscope image to maximize a gray value at a central axis of regions corresponding to a design pattern and a scanned pattern; and step S4, performing registration according to the central axis of the design pattern and the scanned pattern. The present invention also provides a system for registering a circuit design layout and a scanning electron microscope image, a circuit design layout and an imaging error calculation method thereof, and an electronic device. The method and system for registering a circuit design layout and a scanning electron microscope image, the circuit design layout and the imaging error calculation method thereof, and the electronic device feature accurate registration and accurate error calculation.
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