首页> 外国专利> PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY

PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY

机译:带有自组装的垂直纳米晶体管通道和门的图形化

摘要

An inductive self-assembly (DSA) material or diblock copolymer for patterning features that ultimately define the gate electrode and channel region of a vertical nanowire transistor based on a single lithographic operation is disclosed. In embodiments, the DSA material is confined within a patterned guide opening using conventional lithography. In embodiments, channel regions and gate electrode materials are aligned with respect to edges of separate regions in the DSA material.
机译:公开了一种用于图案化特征的电感自组装(DSA)材料或二嵌段共聚物,所述特征基于单个光刻操作最终限定了垂直纳米线晶体管的栅电极和沟道区。在实施例中,使用常规光刻将DSA材料限制在图案化的引导开口内。在实施例中,沟道区域和栅电极材料相对于DSA材料中的分离区域的边缘对齐。

著录项

  • 公开/公告号KR102078071B1

    专利类型

  • 公开/公告日2020-04-07

    原文格式PDF

  • 申请/专利权人 인텔 코포레이션;

    申请/专利号KR20157015581

  • 申请日2013-06-20

  • 分类号H01L21/8234;H01L29/06;H01L29/16;H01L29/423;H01L29/66;H01L29/775;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 11:05:17

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