Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA)

摘要

Semiconductor industry seems to approach a wall where physical geometry and power density issues could possibly render the device fabrication infeasible. Quantum-dot Cellular Automata (QCA) is a new nanotechnology that claims to offer the potential of manufacturing even denser integrated circuits, which can operate at high frequencies and low power consumption. In QCA technology, the signal propagation occurs as a result of electrostatic interaction among the electrons as opposed to flow to the electrons in a wire. The basic building block of QCA technology is a QCA cell which encodes binary information with the relative position of electrons in it. A QCA cell can be used either as a wire or as logic. In QCA, the directionality of the signal flow is controlled by phase-shifted electric field generated on a separate layer than QCA cell layer. This process is called clocking of QCA circuits. The logic realization using regular structures such as PLAs have played a significant role in the semiconductor field due to their manufacturability, behavioral predictability and the ease of logic mapping. Along with these benefits, regular structures in QCAu27s would allow for uniform QCA clocking structure. The clocking structure is important because the pioneers of QCA technology propose it to be fabricated in CMOS technology. This thesis presents a detailed design implementation and a comparative analysis of logic realization using regular structures, namely Shannon-Lattices and PLAs for QCAs. A software tool was developed as a part of this research, which automatically generates complete QCA-Shannon-Lattice and QCA-PLA layouts for single-output Boolean functions based on an input macro-cell library. The equations for latency and throughput for the new QCA-PLA and QCA-Shannon-Lattice design implementations were also formulated. The correctness of the equations was verified by performing simulations of the tool-generate layouts with QCADesigner. A brief design trade-off analysis between the tool-generated regular structure implementation and the unstructured custom layout in QCA is presented for the full-adder circuit.