On-chip data communication : analysis, optimization and circuit design

摘要

On-chip data communication is an active research area, as interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. In this thesis, interconnects are analyzed and techniques and circuits are discussed that can improve their behavior for data communication.udIt is shown that the bandwidth of interconnects is either limited by their distributed RC behavior (for long interconnects), or by the skin-effect. The aggregate bandwidth per cross-sectional area can be optimized by choosing all cross-sectional dimensions roughly equal. The bandwidth of a single interconnect can be increased by using resistive (or resistive-inductive) receiver termination or capacitive transmitter termination. The crosstalk can be mitigated with twisted differential interconnects. With the aid of a symbol response analysis method, it is shown that simple equalization schemes are very effective to boost the achievable data rate, more so than multi-level signaling or band-pass modulation. udTo validate the concepts two demonstrator ICs were developed, both using 10mm long interconnects. The first chip, in a 130nm CMOS process, showed that a combination of pulse-width pre-emphasis, twisted interconnects and low-ohmic receiver termination can boost the data rate to 3Gb/s/ch (at 2pJ/bit), while a conventional transceiver reached only 0.55Gb/s/ch. The second test-chip, in 90nm CMOS, showed that a combination of a capacitive transmitter and a low-power sense-amplifier with DFE at the receiver can reduce the energy consumption to 0.28pJ/bit (at 2Gb/s), much lower than competing designs. udCircuit simulations show that a capacitive transmitter and a low-power sense amplifier can also be very effective as transceivers in a Network on Chip (NoC), with data rates in excess of 9Gb/s (at 130fJ/transition) over 2mm interconnects. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6σ offset reliability at 5 Gb/s.