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Silicon nanowires and silicon/molecular interfaces for nanoscale electronics

机译:用于纳米级电子学的硅纳米线和硅/分子界面

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摘要

This thesis describes the utilization of silicon nanowires and molecular films towards the realization of nanoscale electronics. The key enabling technology is the method in which the silicon nanowires are produced—the superlattice nanowire pattern transfer (SNAP) method. The SNAP method allows for the simultaneous formation and alignment of metal or semiconducting nanowires using a template-mediated approach. ududHigh-performance n- and p-type silicon nanowire field-effect transistors (FETs) were demonstrated. These FETs exhibited consistent performance and strong performance metrics such as high on/off ratios, high on-currents, high mobilities and low subthreshold swings. Due to the nanowire’s large surface-area-to-volume ratio, surface states were shown to dominate performance, especially for the n-type FETs. Reducing the number of surface states improved performance significantly.ududN- and p-type silicon nanowire FETs were integrated into complementary symmetry (CS) logic circuits. This required the development of a pattern doping technique that allowed for spatial control of doped regions. The inverter circuit was fabricated and tested. A gain of ~ 5 was consistently measured from 7 working inverter circuits. This demonstration provided the foundation for the eventual fabrication and characterization of the other Boolean logic functions. ududA methodology was developed that optimizes the design of high-performance logic circuits constructed from Si NW p- and n-type FETs. Circuit performance can be predicted from individual fabricated NW FETs before prototype circuits are manufactured, resulting in a faster and more efficient design process. These results suggest design options for fabricating high performance NW circuits, which can then be implemented experimentally. The effectiveness of this methodology is shown by optimizing the gain of Si NW complementary symmetry inverter from an initially measured value of 8 to a gain of 45.ududLastly, methods to covalently attach electronically interesting molecules via microcontact printing onto gold and silicon substrates were developed. In these studies, the Cu(I)-catalyzed azide-alkyne cycloaddition (CuAAC) reaction was used to form the covalent attachment. It was observed that the reaction would proceed readily by replacing the Cu catalyst in the stamp ink by a Cu coating on the stamp directly. This reaction proceeded quickly on both azide-terminated monolayers on Au and Si(111) substrates.
机译:本文描述了硅纳米线和分子膜在实现纳米级电子学中的应用。关键的使能技术是生产硅纳米线的方法-超晶格纳米线图案转移(SNAP)方法。 SNAP方法允许使用模板介导的方法同时形成和排列金属或半导体纳米线。 ud ud展示了高性能的n型和p型硅纳米线场效应晶体管(FET)。这些FET表现出一致的性能和强大的性能指标,例如高通/断比,高导通电流,高迁移率和低亚阈值摆幅。由于纳米线的表面积与体积之比大,因此表面状态显示出主要性能,尤其是对于n型FET。减少表面状态的数量可以显着提高性能。 ud udN型和p型硅纳米线FET已集成到互补对称(CS)逻辑电路中。这需要开发一种图案掺杂技术,该技术允许对掺杂区域进行空间控制。逆变器电路已经制作和测试。从7个正常工作的逆变器电路中获得的恒定增益约为5。该演示为最终构造和表征其他布尔逻辑功能提供了基础。 ud ud开发了一种方法,可以优化由Si NW p型和n型FET构成的高性能逻辑电路的设计。可以在制造原型电路之前通过单独制造的NW FET预测电路性能,从而实现更快,更高效的设计过程。这些结果提出了制造高性能NW电路的设计选择,然后可以通过实验实现。通过将Si NW互补对称逆变器的增益从最初的测量值优化为8到增益45,可以证明这种方法的有效性。最后,通过微接触印刷将电子感兴趣的分子共价附着到金和硅衬底上的方法被开发。在这些研究中,使用Cu(I)催化的叠氮化物-炔烃环加成(CuAAC)反应形成共价连接。观察到,通过直接在压模上涂覆Cu来代替压模油墨中的Cu催化剂,该反应将容易进行。该反应在Au和Si(111)衬底上的两个叠氮化物封端的单层膜上快速进行。

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    Sheriff Bonnie Ann;

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  • 年度 2009
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