The objective of this research work was to evaluate and test the Read Prediction Buffer integrated circuit (IC). This IC attempts to decrease main- memory latency by predicting the next data cache read miss address and pre- fetching the data before the miss actually occurs in the cache. The motivation for its testing is that, if correct, the chip will significantly improve the speed of imbedded microprocessors which are so prevalent in modern equipment. The approach taken, was to place the RPB between a Pattern Generator Module and a State- Timing logic Analysis Module. The pattern generator was programmed to generate test cases. The output signals of this module were applied to the input pins of the chip. The chip's response was then captured and analyzed using the logic analysis module. Results showed that the chip worked correctly and fully implemented the intended algorithm. However, an evaluation of its architecture indicated two major problems; (a) The RPB provides an additional level of latency to the memory structure when a predicted address is in error, (b) Every time there is a displacement change (which occurs at branches) the RPB predicted address will be in error. These two factors forced the redesign of the RPB, giving birth to the Predictive Read Cache. In the PRC, the first problem was solved by reallocating the chip's position in the memory hierarchy. The IC was converted from a memory controller device to a snooping device. The second problem was eliminated by increasing the number of predictive lines from 1 to 128. This means that the PRC is now able to track 128 different displacements. (KAR) P. 2-3
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