Many computationally intensive scientific applications involve repetitive floating point operationsudother than addition and multiplication which may present a significant performance bottleneck due to theudrelatively large latency or low throughput involved in executing such arithmetic primitives on commodity processors. A promising alternative is to execute such primitives on Field Programmable Gate Arrayud(FPGA) hardware acting as an application-specific custom co-processor in a high performance reconfigurable computing platform. The use of FPGAs can provide advantages such as fine-grain parallelism butudissues relating to code development in a hardware description language and efficient data transfer to andudfrom the FPGA chip can present significant application development challenges. In this paper, we discussudour practical experiences in developing a selection of floating point hardware designs to be implementedudusing FPGAs. Our designs include some basic mathematical library functions which can be implementedudfor user defined precisions suitable for novel applications requiring non-standard floating point representation. We discuss the details of our designs along with results from performance and accuracy analysis tests.
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