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A mixed-signal feed-forward neural network architecture with on-chip learning in CMOS 0.18 microns.

机译:一种混合信号前馈神经网络体系结构,具有CMOS 0.18微米的片上学习功能。

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摘要

One of the main characteristics of the neural networks is their high number of interconnections between the neurons through synaptic multipliers. Interconnections occupy large area and increase the circuit complexity which limits the size of the fully parallel network. To implement large size networks, time-multiplexing should be used. Two new mixed-signal time-multiplexed architectures are proposed for on-chip mixed-signal neural networks. MRIII is used for training the network which is more robust to mixed-signal designs. The problem of node addressing and routing is solved by performing the operations in current mode. The architectures are simple and compact and learning is performed on-chip without the host computer, which reduces the cost of learning for the network. Mixed-signal MDACs are used for synaptic multiplication. A new compact architecture is proposed for the MDAC to reduce the area, power consumption and noise. The proposed MDAC performs the digital to analog conversion in series. Comparison shows that the new MDAC is more linear and has less noise than the conventional MDAC. The layout of the proposed MDAC is relatively easy, since it has a repetitive structure. For the first time, a new 12-bit MDAC is implemented, which enables us to perform on-chip training. The proposed 12-bit MDAC still occupies less area compared to the 7-bit conventional MDAC. A new low-voltage class-AB high-drive buffer for driving the voltages off-chip is developed. The proposed buffer is able to drive capacitive loads up to 2nF. It also drives resistive loads down to 2kO from rail to rail. For compensation, a 0.2pF capacitor is used.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses u26 Major Papers - Basement, West Bldg. / Call Number: Thesis2002 .M47. Source: Masters Abstracts International, Volume: 42-01, page: 0298. Adviser: M. Ahmadi. Thesis (M.A.Sc.)--University of Windsor (Canada), 2003.
机译:神经网络的主要特征之一是它们通过突触倍增器在神经元之间的大量互连。互连占用大面积并增加了电路复杂性,从而限制了完全并行网络的大小。要实现大型网络,应使用时间复用。针对片上混合信号神经网络,提出了两种新的混合信号时分复用架构。 MRIII用于训练网络,该网络对于混合信号设计更为可靠。通过在当前模式下执行操作,可以解决节点寻址和路由的问题。该架构简单而紧凑,无需主机即可在芯片上进行学习,从而降低了网络学习的成本。混合信号MDAC用于突触乘法。为MDAC提出了一种新的紧凑型架构,以减少面积,功耗和噪声。拟议的MDAC串行执行数模转换。比较表明,与常规MDAC相比,新的MDAC具有更高的线性度和更低的噪声。提议的MDAC的布局相对容易,因为它具有重复的结构。首次实现了新的12位MDAC,这使我们能够执行片上培训。与7位常规MDAC相比,建议的12位MDAC仍然占用较少的面积。开发了用于驱动片外电压的新型低压AB类高驱动缓冲器。建议的缓冲器能够驱动高达2nF的电容性负载。它还可以将铁轨之间的电阻性负载降低至2kO。为了补偿,使用了一个0.2pF的电容器。电气和计算机工程系。莱迪图书馆的纸质副本:论文主要论文-西楼地下室。 /电话号码:Thesis2002 .M47。资料来源:国际硕士摘要,第42卷,第0298页,顾问:M. Ahmadi。论文(硕士)-温莎大学(加拿大),2003。

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    Mirhassani Mitra.;

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