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Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform

机译:使用高性能可重构平台实时仿真动态车辆模型

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摘要

A purely software-based approach for Real-Time Simulation (RTS) may have difficulties in meeting real-time constraints for complex physical model simulations. In this paper, we present a methodology for the design and im-plementationofRTS algorithms,basedontheuseof Field-ProgrammableGateArray(FPGA) technologytoimprove the response time of these models. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement is obtained through the use of custom accelerators for common non-linear functions. Since the systems we examined had relatively low response time requirements, our approach greatly simplifies the software components by porting the computationally complexregionsto hardware.We illustratethe partitioningofa hardware-based simulator design across dual FPGAs, initiateRTS usinga system input froma Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transferof simulation results backovera socket, showsa speedup of 2× as compared to a simi-lar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.
机译:纯粹基于软件的实时仿真(RTS)方法可能难以满足复杂物理模型仿真的实时约束。本文基于现场可编程门阵列(FPGA)技术,提出了一种RTS算法的设计和实现方法,以改善这些模型的响应时间。我们的方法利用传统的硬件/软件协同设计方法为基于FPGA的仿真器生成异构架构。对硬件设计进行了优化,以使其有效利用了FPGA的并行特性,并流水线进行了独立的操作。通过将自定义加速器用于常见的非线性功能,可以进一步增强性能。由于我们检查的系统对响应时间的要求相对较低,因此,我们的方法通过将计算复杂的区域移植到硬件上,大大简化了软件组件。 (HIL)框架,并使用我们基于FPGA的平台中的这些仿真结果进行响应分析。总的仿真时间,包括通过套接字接收系统输入(不使用HIL),软件初始化,硬件计算以及将仿真结果转移回套接字所需的时间,与类似的设置相比,速度提高了2倍。没有硬件加速。硬件仿真输出的正确性也已通过纯软件设计的仿真结果进行了验证。

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