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Design and Optimization of InterCell Transformers for Parallel MultiCell Converters

机译:并行多单元转换器的单元间变压器的设计和优化

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摘要

In recent years, the interest for parallel multicell converters has grown, which is partially due to the possibility of coupling the inductors used to connect the different commutation cells together. Coupling the inductors to form an InterCell Transformer (ICT) does not usually modify the output current, but it reduces the current ripple in the windings and the flux swing in some regions of the core. It can be shown that this brings a reduction of copper and core losses in the magnetic component. The reduction of the phase current ripple also reduces the difference between turn on and turn off current in the switches, which brings a reduction of switching losses for devices generating more losses at turn off than at turn on. The design of an ICT is not that different from any other magnetic component but it is very specific and inherent features must be taken into account. Taking full benefit of the potential advantages of ICTs requires the development of special tools and methods which are the focus of the study. We show how to design ICTs considering several topologies and different methods, from the most precise and time-consuming to the less accurate but more quickly calculated. The explanation of the ICT design is divided in four main parts: Copper Losses, Core Losses, Flux Density Saturation and Thermal Aspects. Further attention is given to high frequency copper losses since complex phenomena such as skin and proximity effects highly influence the ICT design. Based on Finite Element Method simulations, smart practices are suggested to reduce high and low frequency copper losses, not only in ICTs but also in inductors and transformers. Simple tables are developed to help transformer designers to identify the best configuration of conductors inside a given core window, depending on the current waveform and frequency, number of turns and geometrical parameters. Optimization routines to reduce the ICT total mass, volume, losses or cost are developed and multidimensional interpolation of pre-simulated values of AC resistance and leakage inductance is used to speed up the optimization routine. Comparison of ICT designs with regard to core and conductor material, number of cells and switching frequency is performed. Comparison with regular inductors is also made in order to verify the benefits of this kind of magnetic component. Multilevel converter control aspects applied to three- hase systems is also investigated in terms of the ICT flux. Zero sequence signals, specific for a PWM strategy and converter/load topology, are created in order to minimize the flux in ICTs and consequently reduce even further the mass and size of these components. Comparison between several PWM methods are performed and experimentally verified.
机译:近年来,对并行多单元转换器的兴趣已经增长,部分原因是由于有可能将用于将不同换向单元连接在一起的电感器耦合在一起。耦合电感器以形成单元间变压器(ICT)通常不会改变输出电流,但会减小绕组中的电流纹波和磁芯某些区域的磁通摆幅。可以证明,这减少了磁性部件中的铜和铁芯损耗。相电流纹波的减小还减小了开关中导通电流与关断电流之间的差异,从而降低了器件的开关损耗,从而使器件在断开时产生的损耗大于在接通时的损耗。 ICT的设计与任何其他磁性组件没有什么不同,但是它非常具体,必须考虑其固有特性。要充分利用ICT的潜在优势,就需要开发特殊的工具和方法,这是研究的重点。我们展示了如何设计ICT,同时考虑几种拓扑和不同方法,从最精确,最耗时的方法到精度较低但计算速度更快的方法。 ICT设计的解释分为四个主要部分:铜损,铁损,磁通密度饱和度和热方面。由于诸如趋肤效应和邻近效应之类的复杂现象会严重影响ICT设计,因此需要进一步关注高频铜损。在有限元方法仿真的基础上,建议采取明智的做法来减少高频和低频铜损,不仅在ICT中,而且在电感器和变压器中。开发了简单的表格,以帮助变压器设计人员根据电流波形和频率,匝数和几何参数,确定给定铁心窗口内导体的最佳配置。开发了减少ICT总质量,体积,损耗或成本的优化例程,并使用了交流电阻和漏感预仿真值的多维插值来加快优化例程。对ICT设计在芯线和导体材料,单元数和开关频率方面进行了比较。还与常规电感器进行了比较,以验证这种磁性元件的好处。还针对ICT通量研究了应用于三急系统的多级转换器控制方面。创建专用于PWM策略和转换器/负载拓扑的零序信号,以最大程度地减小ICT中的通量,从而进一步减小这些组件的质量和尺寸。比较了几种PWM方法并进行了实验验证。

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    Cougo França Bernardo;

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  • 年度 2010
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