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Desenvolvimento de um sensor 'On-Chip' para monitoramento do envelhecimento de SRAMs

机译:开发用于监视SRAM老化的“片上”传感器

摘要

Advances in Complementary Metal-Oxide Semiconductor (CMOS) technology have made possible the integration of millions of transistors into a small area, allowing the increase of circuits' density. In more detail, technology scaling caused the reduction of the transistors' delay, which has resulted in a signi cantly performance improvement of Integrated Circuits (ICs). Furthermore, the increase in the integration level of ICs allowed the development of ICs able to include an increasing number of functions, which in turn increased signi cantly their complexity. In parallel, the rapidly increasing need to store more information results in the fact that the Static Random Access Memory (SRAM) can occupy great part of the System-on-Chip (SoC) silicon area. This is con rmed by the SIA Roadmap which forecasts a memory density approaching 94% of the SoC area in about 10 years [1]. Consequently, memory has become the main responsible of the overall SoC area. However, the reduction of transistor size has introduced several reliability concerns that need to be a ronted by the adoption of di erent optimization techniques. In this context it is important to highlight the phenomenon known as Negative Bias Temperature Instability (NBTI), which a ects the reliability of the ICs along their lifes. Speci cally in the SRAMs NBTI causes degradation of the Static Noise Margim(SNM) which a ects the storage capacity of the memory cells. In this context, the main goal of this thesis is to specify, implement, validate and evaluate a hardware-based technique able to monitor the aging of SRAM cells in order to guarantee their reliability of during the lifetime. The proposed technique is based on an on-chip sensor capable of monitoring dynamic power consumption of the cells during write operations in order to compare them with the value set as default to a new cell. Finally, the proposed methodology has been functionally validated and its e ciency has been evaluated based on the analysis of its monitoring and detection capabilities and from the analysis of the introduced overheads as well as its immunity to the manufacturing process variation.
机译:互补金属氧化物半导体(CMOS)技术的进步使得将数百万个晶体管集成到较小的区域成为可能,从而增加了电路的密度。更详细地讲,技术缩放导致晶体管延迟的减少,从而导致集成电路(IC)的性能显着改善。此外,IC集成度的提高允许开发具有更多功能的IC,从而大大增加了它们的复杂性。同时,快速增长的存储更多信息的需求导致以下事实:静态随机存取存储器(SRAM)会占据片上系统(SoC)硅片区域的很大一部分。 SIA路线图证实了这一点,该路线图预测大约10年内内存密度将接近SoC面积的94%[1]。因此,内存已成为整个SoC领域的主要负责人。然而,晶体管尺寸的减小已经引入了一些可靠性问题,这些问题需要通过采用不同的优化技术来解决。在这种情况下,重要的是要强调被称为负偏置温度不稳定性(NBTI)的现象,该现象会影响IC在其整个生命周期内的可靠性。 SRAM NBTI中的特殊情况会导致静态噪声Margim(SNM)下降,从而影响存储单元的存储容量。在这种情况下,本论文的主要目标是指定,实现,验证和评估一种基于硬件的技术,该技术能够监视SRAM单元的老化,以保证其在使用寿命期间的可靠性。所提出的技术基于片上传感器,该片上传感器能够监视写操作期间单元的动态功耗,以便将其与默认设置为新单元的值进行比较。最后,所提出的方法已在功能上得到验证,并基于对它的监视和检测能力的分析,对引入的间接费用的分析及其对制造工艺变化的抵抗力,对其效率进行了评估。

著录项

  • 作者

    Ceratti Arthur Denicol;

  • 作者单位
  • 年度 2012
  • 总页数
  • 原文格式 PDF
  • 正文语种 Português
  • 中图分类

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