Performance growth in microelectronics, as described by Moore?s law, is steadilyapproaching its limits. Nanoscale technologies are increasingly being explored as apractical solution to sustaining and possibly surpassing current performance trends ofmicroelectronics. This work presents an in-depth analysis of the impact on performance,of incorporating reliability schemes into the architecture of a crossbar molecular switchnanomemory and demultiplexer. Nanoelectronics are currently in their early stages, andso fabrication and design methodologies are still in the process of being studied anddeveloped. The building blocks of nanotechnology are fabricated using bottom-upprocesses, which leave them highly susceptible to defects. Hence, it is very important thatdefect and fault-tolerant schemes be incorporated into the design of nanotechnologyrelated devices.In this dissertation, we focus on the study of a novel and promising class ofcomputer chip memories called crossbar molecular switch memories and theirdemultiplexer addressing units. A major part of this work was the design of a defect andfault tolerance scheme we called the Multi-Switch Junction (MSJ) scheme. The MSJ scheme takes advantage of the regular array geometry of the crossbar nanomemory tocreate multiple switches in the fabric of the crossbar nanomemory for the storage of asingle bit.Implementing defect and fault tolerant schemes come at a performance cost to thecrossbar nanomemory; the challenge becomes achieving a balance between devicereliability and performance. We have studied the reliability induced performance penaltiesas they relate to the time (delay) it takes to access a bit, and the amount of powerdissipated by the process. Also, MSJ was compared to the banking and error correctioncoding fault tolerant schemes. Studies were also conducted to ascertain the potentialbenefits of integrating our MSJ scheme with the banking scheme. Trade-off analysisbetween access time delay, power dissipation and reliability is outlined and presented inthis work.Results show the MSJ scheme increases the reliability of the crossbarnanomemory and demultiplexer. Simulation results also indicated that MSJ works verywell for smaller nanomemory array sizes, with reliabilities of 100% for molecular switchfailure rates in the 10% or less range.
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