The scaling of VLSI technology has spurred a rapid growth in the semiconductorindustry. With the CMOS device dimension scaling to and beyond 90nm technology,it is possible to achieve higher performance and to pack more complex functionalitieson a single chip. However, the scaling trend has introduced drastic variation ofprocess and design parameters, leading to severe variability of chip performance innanometer regime. Also, the manufacturing community projects CMOS will scale forthree to four more generations. Since the uncertainties due to variations are expectedto increase in each generation, it will significantly impact the performance of designand consequently the yield.Another challenging issue in the nanometer IC design is the high power consumptiondue to the greater packing density, higher frequency of operation and excessiveleakage power. Moreover, the circuits are usually over-designed to compensate foruncertainties due to variations. The over-designed circuits not only make timing closuredifficult but also cause excessive power consumption. For portable electronics,excessive power consumption may reduce battery life; for non-portable systems itmay impose great difficulties in cooling and packaging.The objective of my research has been to develop design methodologies to addressvariations and power dissipation for reliable circuit operation. The proposed workhas been divided into three parts: the first part addresses the issues related withpower/ground noise induced by clock distribution network and proposes techniques to reduce power/ground noise considering the effects of process variations. The secondpart proposes an elastic pipeline scheme for random circuits with feedback loops. Theproposed scheme provides a low-power solution that has the same variation toleranceas the conventional approaches. The third section deals with discrete buffer and wiresizing for link-based non-tree clock network, which is an energy efficient structure forskew tolerance to variations.For the power/ground noise problem, our approach could reduce the peak currentand the delay variations by 50% and 51% respectively. Compared to conventionalapproach, the elastic timing scheme reduces power dissipation by 20% ? 27%. Thesizing method achieves clock skew reduction of 45% with a small increase in powerdissipation.
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