Multi-physics investigation on the failure mechanism and short-time scale wave motion in flip-chip configuration

摘要

The demands for higher clock speeds and larger current magnitude in high-performance flip-chip electronic packaging configurations of small footprint have inevitably raised the concern over rapid thermal transients and large thermal spatial gradients that could severely compromise package performance. Coupled electrical-thermal-mechanical multi-physics were explored to evaluate the concern and to establish the knowledge base necessary for improving flip-chip reliability. It was found that within the first few hundred nanoseconds upon power-on, there were fast attenuating, dispersive shock waves of extremely high frequency propagating in the package. The notions of high cycle fatigue, power density and joint time-frequency analysis were employed to characterize the waves and the various failure modes associated with the moving of these short-lived dynamical disturbances in bulk materials and along interfaces. A qualitative measure for failure was also developed which enables the extent of damages inflicted by short-time wave propagation to be calculated in the probability sense. Failure modes identified in this study are all in agreement with what have been observed in industry. This suggests that micron cracks or interfacial flaws initiated at the short-time scale would be further propagated by the CTE-induced thermal stresses at the long-time scale and result in eventual electrical disruptions. Although epoxy-based underfills with fillers were shown to be effective in alleviating thermal stresses and improving solder joint fatigue performance in thermal cycling tests of long-time scale, underfill material viscoelasticity was found to be insignificant in attenuating short-time scale wave propagation. On the other hand, the inclusion of Cu interconnecting layers in flip-chips was shown to perform significantly better than Al layers in suppressing short-time scale effects. These results imply that, if improved flip-chip reliability is to be achieved, all packaging constituent materials need to be formulated to have well-defined short-time scale and long-time scale properties. In addition, the results also suggest that the composition and layout of all packaging components be optimized to achieve discouraging or suppressing short-time scale dynamic effects. In summary, results reported herein and numerical procedures developed for the research would not just render higher packaging manufacturing yield, but also bring out significant impact on packaging development, packaging material formulation and micro-circuit layout design.