Frequency synthesizer is a key building block of fully-integrated wireless communicationsystems. Design of a frequency synthesizer requires the understanding ofnot only the circuit-level but also of the transceiver system-level considerations. Thisdissertation presents a full cycle of the synthesizer design procedure starting from theinterpretation of standards to the testing and measurement results.A new methodology of interpreting communication standards into low level circuitspecifications is developed to clarify how the requirements are calculated. Adetailed procedure to determine important design variables is presented incorporatingthe fundamental theory and non-ideal effects such as phase noise and referencespurs. The design procedure can be easily adopted for different applications.A BiCMOS frequency synthesizer compliant for both wireless local area network(WLAN) 802.11a and 802.11b standards is presented as a design example. The twostandards are carefully studied according to the proposed standard interpretationmethod. In order to satisfy stringent requirements due to the multi-standard architecture,an improved adaptive dual-loop phase-locked loop (PLL) architecture isproposed. The proposed improvements include a new loop filter topology with anactive capacitance multiplier and a tunable dead zone circuit. These improvementsare crucial for monolithic integration of the synthesizer with no off-chip components.The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling timeperformance while making it more suitable for monolithic integration. It opens anew possibility of using an integer-N architecture for various other communicationstandards, while maintaining the benefit of the integer-N architecture; an optimalperformance in area and power consumption.
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