高性能直接数字式低频率合成器设计

摘要

针对采用当前方法进行高性能直接数字式低频率合成器设计时,难以计算出直接数字式低频率合成器的查找表地址的宽度,存在输出频率分辨率较低、相位噪声较高的问题,提出一种基于FPGA的高性能直接数字式低频率合成器设计方法.该方法对直接数字式低频率合成器原理进行分析,得到直接数字式低频率合成器的正弦波公式,在此基础上采用进位链与流水线技术相结合的方法计算查找表地址输入的宽度,得到满足查找表内的数据长度范围,并结合相位累加器对数字式锯齿波进行输出,获取数字式锯齿波的若干相位作为ROM的地址输入,然后对输入地址进行查表以及运算处理,由此完成高性能直接数字式低频率合成器设计.实验结果表明所提方法能够有效提高直接数字式低频率合成器的频率分辨率,同时具有较强的抵抗相噪能力.%The current method used to design the high-performance direct digital low-frequency synthesizer is difficult to calculate the address width of the lookup table of the direct digital low-frequency synthesizer,which has low resolution of output frequency and high phase noise. Therefore,a design method of high-performance direct digital low-frequency synthesizer based on FPGA is proposed. The principle of the direct digital low-frequency synthesizer is analyzed to obtain the sine wave formula of the synthesizer. On this basis,the method combining the carry chain with pipelining technology is used to calculate the width of input address of the lookup table to get the data length range satisfying lookup table. The phase accumulator is combined to out-put the digital sawtooth wave to get some phases of digital sawtooth as the input addresses of ROM,and then the table lookup and calculation are carried out for the input addresses to accomplish the design of the high-performance direct digital low-fre-quency synthesizer. The experimental results show that the method can improve the frequency resolution of the direct digital fre-quency low-frequency synthesizer effectively,and has strong ability to resist phase noise.