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High Performance Reversible Direct Data Synthesizer for Radio Frequency Applications

机译:用于射频应用的高性能可逆直接数据合成器

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Design of Reversible logic gate enabled Reconfigurable Direct digital synthesizer is evaluated here. The need for Direct Digital Synthesizers (DDS) inherently finds application in the area of radio frequency communication. DDS is a method of producing an analog waveformusually a sine waveby generating a time-varying signal in digital form and then performing a digital-to-analog conversion. The proposed design presents an important analysis based on Reversible logic gates for the application of DDS which is a powerful device employed to produce standard signal sweeps from lowest frequency to highest frequency. The sweeps of DDS frequency depends on the configurable frequency words produced by high speed Field Programmable Gate Array (FPGA) platforms. Because operations within DDS devices are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today's DDS devices are very compact and draw little power. Here the proposed system focuses on development of DDS through Artificial Intelligence (AI) with Field Programmable Gate Array (FPGA) devices. The primary need for FPGA and AI combination provides the replacement of analog Phase Locked Loop (PLL) in traditional DDS circuits. The fully digital architecture enable the system able to configure the digital PLL developed inside the FPGA core. Low noise and Low power factor is being achieved through low power techniques utilized in the architecture development part. The proposed system increase the sweep frequency resolution, Reverse fluctuations through leakage voltage etc.
机译:本文评估了启用可逆逻辑门的可重配置直接数字合成器的设计。本质上,对直接数字合成器(DDS)的需求在射频通信领域得到了应用。 DDS是一种通过产生数字形式的时变信号然后执行数模转换来产生模拟波形(通常为正弦波)的方法。提出的设计针对DDS的应用提出了基于可逆逻辑门的重要分析,DDS是一种强大的设备,可用于产生从最低频率到最高频率的标准信号扫描。 DDS频率的扫描取决于高速现场可编程门阵列(FPGA)平台产生的可配置频率字。由于DDS设备内的操作主要是数字操作,因此它可以在输出频率之间快速切换,提供精细的频率分辨率以及在广泛的频率范围内运行。随着设计和处理技术的进步,当今的DDS设备非常紧凑且功耗很小。在这里,拟议的系统着重于通过具有现场可编程门阵列(FPGA)器件的人工智能(AI)开发DDS。 FPGA和AI结合的主要需求是替代传统DDS电路中的模拟锁相环(PLL)。全数字架构使系统能够配置在FPGA内核内部开发的数字PLL。低噪声和低功率因数是通过在架构开发部分中使用的低功率技术来实现的。拟议的系统提高了扫描频率分辨率,通过泄漏电压产生的反向波动等。

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