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Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization

机译:重叠FinFET结构中栅极条纹引起的势垒降低及其优化

摘要

The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I-on. We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si3N4 spacers, with kappa = 20 spacers, we show that it is possible to achieve an 80% increase in I-on at iso-I-off conditions and a 15% decrease in the inverter delay for a fan-out of four.
机译:在FinFET的源极/漏极下重叠区中难以制造和控制精确定义的掺杂分布的困难使得随着技术的发展,必须使用未掺杂的栅极下重叠区。我们提出了一种现象,即在具有未掺杂的下重叠区域的FinFET中,栅极条纹引起的势垒降低(GFIBL)。在这些FinFET中,我们证明了GFIBL可以有效地用于改善I-on。我们建议在此类FinFET中使用高kappa间隔物,以增强GFIBL的效果,从而获得更好的器件和电路性能。当与具有Si3N4垫片的下叠式FinFET相比,kappa = 20垫片时,我们表明在等压关断条件下,I-on可以增加80%,而逆变器延迟可以降低15%。扇出四个。

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