CMOS technology has continuously scaled into deep sub-micron regime. With CMOS scaling, many complex design issues arise. The challenges include, but not limited to, the increasing of interconnect delay and power, exponential growth of leakage power, and rapid growth of design complexity. These challenges motivate us to design new CAD algorithms to reduce power consumption (both leakage power and dynamic power), to effectively reduce design complexity, and to improve circuit performance.In Chapter 2, we present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of moves form the basis of the new simulated annealing based algorithm. In Chapter 3, we present the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources, such as Configurable Logic Blocks (CLB), RAMs and multipliers. In Chapter 4, we present an efficient and effective method to reduce circuit leakage power consumption using input vector control. Our algorithm is able to solve the IVC and gate replacement problems simultaneously. A dynamic programming based-algorithm is used for making fast evaluation on input vectors, as well as replacing gates. In Chapter 5, we present an FPGA technology mapping algorithm targeting dynamic power minimization. We propose a switching activity estimation model considering glitches for FPGAs, and develop our technology mapping algorithm based on this model. In Chapter 6, we present an FPGA technology mapping algorithm targeting designs with multi-clock domains such as those containing multi-clocks, multi-cycle paths, and false paths. We use timing constraints to handle these unique clocking issues. Our algorithm produces a mapped circuit with the optimal mapping depth under timing constraints. In chapter 7, we target FPGA performance optimization using a novel BDD-based synthesis approach. In this work, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization.
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