Design Guide for CMOS-On-SIMOX. Test Chips NIST3 and NIST4

摘要

The design guidelines for test chips NIST 3 and NIST4 are specified in thismanual. These chips were designed for process monitoring and device parameter extraction for a CMOS (Complementary Metal-Oxide-Semiconductor)-on-SOI (Silicon-On-Insulator) process. The chips contain structures which are common to a standard CMOS process as well as structures specifically designed for a SIMOX (Separation by the IMplantation of OXygen) process. In order to facilitate the CAD process, a unique 'technology file' was created for the Magic VLSI layout editor used on a Sun-3/280 system running Sun Version 3.5. This SIMOX technology file is very general and can be used to build CMOS as well as SIMOX chips. NIST3 is 6380 micrometers x 4780 micrometers and contains several large-geometry MOSFETs, resistors, and capacitors. NIST4 is 1 cm x 1 cm and contains approximately 300 small-geometry test structures. The SIMOX specific structures found on these chips include MOSFETs, capacitors, interconnects, and pads to be discussed in more detail. The test guide for the test structures on NIST3 and NIST4 is included in a separate manual (PB93-152106).