Test Guide for CMOS-On-SIMOX Test Chips NIST3 and NIST4.

摘要

A test chip set has been designed for process monitoring and device parameter extraction for a CMOS (Complementary Metal-Oxide-Semiconductor)-on-SOI (Silicon-On-Insulator) process. The chips contain structures which are common to a standard CMOS process as well as structures specifically designed for a SIMOX (Separation by the IMplantation of OXygen) process. NIST3 is 6380 micrometers x 4780 micrometers and contains several large-geometry MOSFETs, resistors, and capacitors. NIST4 is 1 cm x 1 cm and contains approximately 300 small-geometry test structures. The SIMOX specific structures found on these chips include MOSFETs, capacitors, interconnects, and pads. The report presents the information necessary to test NIST3 and NIST4. Design guidelines, technology file modifications, and data output specifications for NIST3 and NIST4 are discussed in a separate manual.