Experimental Investigation of a Shielded Complementary Metal-Oxide Semiconductor (Mos) Structure

摘要

A shielded integrated complimentary MOS transistor structure is described which is used to prevent field inversion in the region not occupied by the gates and which permits the use of a thinner field oxide, reduces the chip area, and has provision for simplified multilayer connections. The structure is used in the design of a static shift register and results in a 20% reduction in area. (Author)