Competition between gettering by implantation-induced cavities in silicon and internal gettering associated with SiO{sub 2} precipitation

摘要

Dissolved or metallic impurities can degrade silicon integrated circuit (IC) device yields when present in the near surface, active device region. This is such a critical issue that the IC community has set specifications for the reduction of metallic impurities down to 2.5 {times} 10{sup 9} atoms/cm{sup 3}. The exceptionally high diffusivity and solubility of Cu and Fe in silicon and their presence in many processing tools makes these impurities of particular interest. Additionally, Cu is being considered as an interconnect material because of its low electrical resistivity which creates a high potential for contamination. Here, the gettering behavior of Cu and Fe was investigated in CZ silicon which contained both internal-gettering sites in the bulk due to SiO{sub 2} precipitation and a device-side layer of cavities formed by He implantation and annealing. The objective was to quantify the effectiveness of impurity gettering at cavities relative to the widely used internal-gettering process. Both rapid thermal anneals and furnace anneals were used during the gettering sequences to reveal transient effects as well as the final, thermodynamically-equilibrated condition. For temperatures of 700, 800 and 850 C, the cavity gettering was observed to predominate over internal gettering as indicated both by the number of gettered atoms in the cavities and the residual solution concentration in the device region. The results are interpreted in detail by numerically solving the diffusion equation with sink-related source terms based on earlier, fundamental studies of the underlying mechanisms of internal and cavity gettering.