Automatic Generation of Reliability Functions for Processor-Memory-Switch Structures

摘要

Reliability computation is gaining much importance for computer system architectures with built in redundancy, such as multiprocessors. The task of computing the reliability function for arbitrary Processor-Memory-Switch (PMS) interconnection structures, however, is tedious and prone to human error. Existing reliability computation programs make one of two assumptions: That the case analysis of success states of the system has been carried out. Such analysis must be done manually. In this instance the input to the program is usually in the form of an intermediate representation (e.g. Fault Tree, Reliability Graph); and That the interconnection structure is a member of, or can be partitioned into, some limited class of structures for which a parametric family of equations exists (e.g. N-Modular Redundant systems, Hybrid Redundant systems). This thesis represents a first step in the development of a methodology for automating the computation of symbolic reliability functions for arbitrary interconnection structures at the PMS level. The work reported here automates the task of case analysis and problem partitioning in the hard-failure reliability computation for PMS structures. As a consequence attention is freed to focus almost wholly on specifying the reliability computation problem. The advantages of such an approach are (i) utility to a larger class of users, not necessarily expert in reliability analysis, and (ii) a lower probability of human error in the computation.