基于多端口存储器互连结构的多处理器系统芯片设计

摘要

One of the important questions is interconnect architecture between multi-processors in design of system on chip. We propose a third kind network on chip interconnect architecture that is multi-port memories-based interconnect architecture behind of the bus-based and switch-based interconnect architecture. We use VHDL design the multi-clock, multi-port memories,serve simulation function of data transfer between multi-processors with EDA tools and analyze the characteristic of bus-based, switch-based, MPM-based interconnect architecture. Research shows the MPM-based interconnect architecture has asynchronous data transfer, data buffer function. It has the strongpoint to cut down latency time of data transfer between processors and the matrix topology of MP-SOC is extendable.%多处理器系统芯片设计的关键问题之一是微处理器之间的互连结构.在总线互连结构和开关互连结构之后,提出了基于多端口存储器的第3种互连结构.利用VHDL进行了多时钟多端口存储器设计,并利用EDA工具进行了片上系统芯片的多微处理器数据通讯的功能仿真.分析了基于总线、基于开关、基于多端口存储器的3种互连结构的特点.研究表明基于多端口存储器的互连结构具有异步数据传输,数据缓冲功能;具有数据传输延时小,多微处理器系统芯片的拓扑阵列规模可扩展的优点.