The NUMA page migration/page replication ASIC {lcub}NPMR{rcub}: A chip design to improve memory system performance in a Non-Uniform Memory Access (NUMA) multiprocessor system architecture.

摘要

In this thesis, an unique ASIC design is presented. The objective of my work is to present this unique HDL based ASIC design, which has the following as the primary design objective: a hardware based (ASIC) solution to improve memory latency in a Non-Uniform Memory Access (NUMA) machine by minimizing accesses to pages located in remote system memory. The NUMA Page Migration/Page Replication (NPMR) ASIC maintains in hardware an array of page migration counters, which are dedicated to measuring and identifying when and which pages should be migrated or replicated from one processor/memory module to another.; My ASIC based solution to page migration/page replication provides the following benefits: (1) For many NUMA systems my chip provides a single chip simple drop in solution for implementing a page migration strategy and thereby enhancing NUMA memory system performance. (2) My chip relieves the operating system of maintaining any page migration counters in software. My ASIC permits the operating system to spend more time and resources running the customers application and less time on running system overhead routines to update counters. (3) page migration is being performed in my ASIC at very high system clock speeds—much faster than operating system software routines. (4) my ASIC is extremely programmable which permits system firmware to configure this chip to optimize its performance for the needs of any specific NUMA system design. (5) My ASIC provides a hardware solution which is encoded in an HDL making the ASIC design very flexible/transferable. (6) My ASIC provides a hardware solution which contains a large amount of logic gates operating at very high clock speeds. This large number of gates permits the ASIC to track a large number a pages in its counter array. The limit is set by the target technology library. I have intentionally architected and partitioned this chip to easily instantiate additional counter arrays and associated control logic so as to take maximum advantage of advanced target technology libraries (more available gate count).; In summary, this thesis presents my unique ASIC design. The objective of this chip is to minimize remote memory references and thereby avoid the large latency associated with remote system memory accesses and thereby improve memory system performance in a Non-Uniform Memory Access (NUMA) multiprocessor system architecture. (Abstract shortened by UMI.)