Arithmetic Circuitry for High Speed VLSI Winograd Fourier Transform Processor

摘要

The objective of this thesis is to define, design, and implement an efficient VLSI architecture which computes the Discrete Fourier Transform using the Winograd Fourier Transform Algorithm. The architecture includes circuitry to perform input/output, WFT calculations, parity checking and generation, and scale factor generation. Keywords: Chips(Electronics); Digital Signal processing.