A high-speed CMOS implementation of the Winograd Fourier transform algorithm

摘要

A technique for partitioning hardware implementations of the Winograd (1976) Fourier transform algorithm (WFTA) into separate modules is presented. Instead of the prime factor algorithm, this technique is based on the Winograd nesting method and thus preserves the minimum number of multiplications in the WFTA. An integrated circuit capable of computing over 2 million 20-point discrete Fourier transforms/s is described. Using five of these integrated circuits, the partitioning technique can be applied to increase the transform length to 60 points.