Introducing Redundancy into VLSI Designs for Yield and Performance Enhancement

摘要

New challenges have been brought to fault-tolerant computing research because of developments in IC technology. One emergent area in VLSI designs is development of architectures, built by interconnecting a large number of a few types of elements on a single chip or wafer. Two important topics, related to such VLSI designs, are the focus of this paper; they are yield enhancement and performance improvement. In this paper we present analytical models that evaluate how yield enhancement and performance improvement may both be achieved by introducing redundancy into these VLSI designs.