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Yield-enhanced routing for high-performance VLSI designs

机译:高性能VLSI设计的良率提高的布线

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Abstract: It is widely recognized that interconnects will be the main bottleneck in enhancing the performance of future deep sub- micron VLSI designs. Interconnects do not `scale' well with decreasing feature sizes and therefore dominate the delays in the integrated circuit. In addition to RC delays, crosstalk noise also contributes significantly to the delays experienced by a signal. Interconnects are more susceptible to manufacturing defects and therefore affect the product yields significantly. Recently, several channel-routing based solutions have been proposed to minimize crosstalk noise and also enhance yield of the routing. While these approaches are effective, they do not provide maximum benefits as they are either constrained by a particular design methodology or are post-routing steps which have limited scope for significant improvement. Also, design for manufacturability objectives have not been fully exploited by VLSI CAD tools as they do not integrate seamlessly into the conventional design flow and the added overheads make it less attractive. In this paper, we proposed a modified routing algorithm that maximizes yield and reduces crosstalk noise while using minimal area for the routing. The yield enhancement objective has been integrated into the routing phase as a preferred constraint (a constraint that will be satisfied only if the primary constraints of minimal area and wire length have been satisfied) and fits well into the conventional design flow. This enables the router to produce an output which provides maximum achievable critical area reduction for the given routing solution. Post-routing layout modification is also done with the objective of minimizing the interaction area between the interconnects by exploiting the gridless property of the router. The above algorithm is incorporated into GLITTER (the gridless, variable width channel router), and the results on channel- rotating benchmarks are presented. These results show a significant reduction in the critical area achievable by using the proposed algorithm.!25
机译:摘要:众所周知,互连将成为增强未来深亚微米VLSI设计性能的主要瓶颈。互连随着特征尺寸的减小而不能很好地“缩放”,因此支配了集成电路中的延迟。除RC延迟外,串扰噪声还对信号所经历的延迟做出了重要贡献。互连更容易受到制造缺陷的影响,因此会严重影响产品良率。最近,已经提出了几种基于信道路由的解决方案,以最小化串扰噪声并提高路由的产量。尽管这些方法有效,但它们不能提供最大的收益,因为它们要么受特定设计方法的约束,要么处于路由后步骤,而这些步骤的显着改进范围有限。此外,VLSI CAD工具还没有完全利用可制造性目标的设计,因为它们无法无缝集成到常规设计流程中,并且增加的开销使其吸引力降低。在本文中,我们提出了一种改进的路由算法,该算法可在最小化布线面积的同时最大化良率并减少串扰噪声。良率提高目标已作为首选约束条件(仅当最小面积和导线长度的主要约束条件得到满足时才会得到满足)已集成到布线阶段中,并且非常适合常规设计流程。这使路由器能够产生输出,从而为给定的路由解决方案提供最大可实现的临界面积减小。路由后布局修改的目的还在于通过利用路由器的无网格特性来使互连之间的交互区域最小化。上面的算法被合并到GLITTER(无网格可变宽度信道路由器)中,并给出了信道旋转基准测试的结果。这些结果表明,使用所提出的算法可以显着减少可达到的临界面积!25

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