Dramatically Improved Radiation Hardness for CMOS Silicon Gate Integrated Circuits Even Down to Cryogenic Temperatures

摘要

This program focuses on Field-Hardness ; specifically, the parasitic N-channel leakages which can result on the edge of an N-Channel transistor from source to drain, from drain of one device to the drain of another or from drain (across the CMOS P-well) to the N-substrate (Vdd). This type of leakage normally causes device failure well before the more publicized gage-oxide problem cause Vt to drift out of spec. By butting a poly field-plate directly next to the device in the width direction (for example) we dramatically minimize the positive charge which can build up during irradiation since there is a minimal amount of oxide under this field plate; this technique is used to extend previously used concepts of using buried P+ guard-rings and special gate/field overlap layout to improve the Radiation Hardness of Integrated Circuits and has the added bonus of obviously not being sensitive to Carrier Freeze-out phenomena which degrades P+ guard-ring usefulness at a cryogenic temperatures.