Fabrication and Electrical Characterization of Multilevel Aluminum Interconnects Used to Achieve Silicon-Hybrid Wafer-Scale Integration

摘要

The purpose of this research was to develop, fabricate, and electrically characterize a wafer-scale process developed for use with the 272-point Prime Factor Algorithm (PFA) processor. This process integrates discrete integrated circuit die in a planarized wafer package. The entire wafer surface was coated with photosensitive polyimide, which was patterned with vias for the interconnect contacts. The two die were electrically interconnected with printed aluminum interconnects using conventional silicon processing equipment. The original goals of this research included a system test to evaluate the interconnect network. However, difficulties in the processing environment only allowed a single interconnect to be parametrically evaluated up to 10 MHz. The aluminum interconnect was 26 micrometers wide and 1.2 micrometers thick. This interconnect exhibited no distinguishable propagation delay and attenuation for a one centimeter path length.