Specification and Design Methodologies for High-Speed Fault-Tolerant Array Algorithms and Structures for VLSI

摘要

For convenience we summarize here the project objectives as stated in the research proposal. This research in the methodologies for the specification and design of high-speed, fault-tolerant VLSI array structures has two related objectives (1) a high-level language approach to the specification and simulation of VLSI algorithms and networks using a functional-style (LISP-like) language (Task 1), and (2) cost-effective methods to introduce fault-tolerance (error detection, fault location, retry, and reconfiguration) into VLSI-implemented systolic systems and similar computing arrays (Task 2).