Structural Computer-Aided Design of Current-Mode CMOS Logic Circuits.

摘要

A set of CAD tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based upon the cost-table method. The general circuit structure, the cost-table functions and the decomposition procedure used in the cost-table synthesis program are explained. The synthesis program is based upon a logically complete set of basic elements for CMCL circuits. After circuit synthesis the actual layout is generated using standard-cell IC design tools.