CMOS current-mode logic gates with controlled logic swing and switching speed

摘要

The speed of CMOS current-mode logic gates 32 are varied by altering their tail currents. The resistances of the PMOS loads in the logic gates are varied in inverse proportion to the tail currents to maintain a constant output voltage swing. The speed of the logic gates is detected by a ring oscillator 84, the output frequency of which is compared with a reference frequency in comparator 86. The integrator 88 and bias generator 34 respond to the frequency error signal to dynamically adjust the tail currents, thereby maintaining logic gate switching speed in correlation with the reference clock frequency. The technique allows process, voltage and temperature (PVT) compensation and ensures reliable logic operation without excessive logic gate power consumption..