A CMOS current-mode logic gate using subthreshold conduction

摘要

A low power CMOS CML logic gate comprises a differential transistor pair M1,M2 operating in weak inversion and switching current to either of a pair of load transistors M3,M4 also operating in weak inversion. The load transistors have short channels (90 nm) and so are subject to drain-induced barrier lowering (DIBL) which reduces output resistance in saturation (figure 5b). This allows the loads to operate linearly for source-drain voltages from zero to voltages above VDSsat so that a higher output logic swing can be obtained. The logic output swing may be stabilized against PVT variation by a bias circuit using a replica gate (figure 4).