Scalable Low-Power Deep Machine Learning with Analog Computation.

摘要

Over the course of this project we have accomplished the primary objective of this seedling project to develop analog computational circuits for deep machine learning. We have performed extensive simulations investigating the magnitude of errors expected from analog computational elements and their impact on the overall learning performance. We have also fabricated and tested a prototype chip, which demonstrates successful execution of an unsupervised machine learning task. We have further designed a second more complex learning chip. We have made significant innovations to the algorithm to facilitate analog implementation. We have also implemented several adaptive circuits in a field-programmable analog array (FPAA).