Formal Description of the Incremental Translation of Stage 2 VHDL into StateDeltas in the State Delta Verification System (SDVS)

摘要

This report documents a formal semantic specification of Stage 2 VHDL, a subsetof the VHSIC Hardware Description Language (VHDL), via translation into the temporal logic of the State Delta Verification System (SDVS). Stage 2 VHDL is the third of successively more sophisticated VHDL subsets to be interfaced to SDVS. The specification is a continuation-style denotational semantics of Stage 2 VHDL in terms of state deltas, the distinguishing logical formulas used by SDVS to describe state transitions. The semantics is basically specified in two phases. The first phase performs static semantic analysis, including type checking and other static error checking, and collects an environment for use by the second phase. The second phase performs the actual translation of the subject Stage 2 VHDL description into state deltas. An abstract syntax tree transformation is interposed between the two translation phases. The translator specification was, for the most part, written in DL, the semantic metalanguage of a denotational semantics specification system called DENOTE. DENOTE enables the semantic equations of the specification to be realized both as a printable representation (included in this report) and an executable Common Lisp program that constitutes the translator's implementation. However, the second phase semantics of the VHDL simulation cycle has a direct operational implementation in the VHDL translator code.