Testing of a Read Prediction Buffer Integrated Circuit and Design of a PredictiveRead Cache

摘要

The objective of this research work was to evaluate and test the Read PredictionBuffer integrated circuit (IC). This IC attempts to decrease main-memory latency by predicting the next data cache read miss address and pre-fetching the data before the miss actually occurs in the cache. The motivation for its testing is that, if correct, the chip will significantly improve the speed of imbedded microprocessors which are so prevalent in modern equipment. The approach taken,