Investigation of asymmetric effects due to gate misalignment, gate bias and underlap length in III-V heterostructure underlap DG MOSFET

摘要

In the present work, we investigate the influence of asymmetry in III-V heterostructure underlap DG MOSFET caused by back gate movement, back gate voltages and drain side underlap length. The device has narrowband In_(0.53)Ga_(0.47)As and wideband InP layers in the channel, along with high-K A1203 as the gate dielectric. The 2D Sentaurus TCAD simulations are done using drift diffusion model and interface traps are considered. The simulation model is calibrated with the previous reported experimental results. For the same gate misalignment value, back gate shift toward drain (BG_D) resulted in a lower DIBL, loff and Delay, than back gate shift towards source (BG_S). Conversely, BG_S results in lower SS, higher on and Ion//loff ratio. Excellent threshold voltage controllability, reduced delay, reduced energy delay product, higher Ion//loff ratio are achieved by varying back gate voltage. Varying drain underlap reduces DIBL, SS, Delay, loff and increases Vt and Ion/loff ratio. Thus, application specific optimized device parameters can be achieved with asymmetrical device structure, asymmetrical gate bias or its combination.