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A comparative study of analog/RF performance: Symmetric and asymmetric underlap gate stack DG-MOSFETs

机译:模拟/ RF性能的比较研究:对称和非对称的下叠栅叠层DG-MOSFET

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Underlap Double Gate MOSFET with Gate Stack architectures show better performance for its enhanced immunity to short channel effects. In this work, the Underlap Double Gate MOSFET with Gate Stack having symmetric and asymmetric source drain configurations have been compared for improved subthreshold analog performance in the 32nm gate length regime. Using the data obtained from 2D numerical simulator Sentaurus TCAD, the parameters such as the on current (Ids), the transconductance (gm), the gain per unit current (gm/Ids), the total gate capacitance (Cgg), the cut off frequency (fT) have been analyzed. Analysis suggested that the average on current, the transconductance, the cut off frequency and the total gate capacitance are increase by 56.86%, 46.73%, 3.5% and 28.25% respectively compared to the SymmetricUndelap Double Gate MOSFET.
机译:具有栅极叠层架构的Underlap双栅极MOSFET表现出更好的性能,因为它增强了对短沟道效应的抵抗力。在这项工作中,已对具有对称和非对称源极漏极配置的栅极叠层的Underlap双栅极MOSFET进行了比较,以改善32nm栅极长度条件下的亚阈值模拟性能。使用从2D数值模拟器Sentaurus TCAD获得的数据,这些参数包括导通电流(Ids),跨导(gm),每单位电流的增益(gm / Ids),总栅极电容(Cgg),截止值频率(fT)已被分析。分析表明,与SymmetricUndelap双栅极MOSFET相比,平均电流,跨导,截止频率和总栅极电容分别增加了56.86%,46.73%,3.5%和28.25%。

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