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首页> 外文期刊>Soldering & Surface Mount Technology >Finite element analysis of flip - chip on board (FCOB) assembly during reflowsoldering process
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Finite element analysis of flip - chip on board (FCOB) assembly during reflowsoldering process

机译:回流焊过程中的倒装板上芯片(FCOB)组件的有限元分析

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Purpose - Out-of-plane displacement (warpage) is one of the major thermomechanical reliability concerns for board-level electronic packaging. The warpage and residual stresses can cause unreliability in the performance of electronic chip. An accurate estimation of the distortion and the residual stresses will help in selecting right combination of material for soldering and to determine the better assembly procedure of the chip. The purpose of this paper is to create a 3D nonlinear finite element model to predict the warpage, bending stresses, shear and peel stresses in a flip-chip on board (FCOB). Design/methodology/approach - A 3D finite element procedure has been developed considering the material nonlinearity during solidification for a FCOB assembly. Finite element results have been compared with the experimental values. Findings - The present finite element method gives better approximation of residual warpage and stresses compared to analytical models available in the literature. Originality/value - The 3D finite element approach considering the elasto-plastic and temperature-dependent material properties has not been attempted by any authors. Experiments have been conducted for the comparison of finite element values. The finite element results compare better than the methods available in the literature. Hence a better method for estimating the deformation and residual stresses in flip-chip assembly has been suggested.
机译:目的-平面外位移(翘曲)是板级电子封装的主要热机械可靠性问题之一。翘曲和残余应力会导致电子芯片性能不可靠。准确估计变形和残余应力将有助于选择正确的焊接材料组合,并确定更好的芯片组装程序。本文的目的是创建一个3D非线性有限元模型,以预测板载倒装芯片(FCOB)中的翘曲,弯曲应力,剪切应力和剥离应力。设计/方法/方法-考虑到FCOB组件在固化过程中材料的非线性,开发了一种3D有限元程序。将有限元结果与实验值进行了比较。发现-与文献中可用的分析模型相比,本发明的有限元方法可以更好地近似残余翘曲和应力。原创性/价值-任何作者都没有尝试过考虑弹塑性和温度相关材料特性的3D有限元方法。已经进行了用于比较有限元值的实验。有限元结果比文献中提供的方法更好。因此,已经提出了一种更好的估计倒装芯片组装中的变形和残余应力的方法。

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