Delay-conscious switch-level modeling of MOS LSI circuits

摘要

The switch-level modeling of digital MOS circuits subject to propagation delay is addressed. The operation of a given circuit is represented in terms of a Petri-net model. This essentially uses a two-level marking, which serves to calculate certain functional parameters of the circuit. The complexity of the Petri net is independent of the circuit functionality but varies with transistor count. This parameter governs the amount of computation in executing the model.