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Au-Sn flip-chip solder bump for microelectronic and optoelectronic applications

机译:用于微电子和光电应用的Au-Sn倒装芯片焊料凸点

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摘要

As an alternative to the time-consuming solder pre-forms and pastes currently used, a co-electroplating method of eutectic Au-Sn alloy was used in this study. Using a co-electroplating process, it was possible to plate the Au-Sn solder directly onto a wafer at or near the eutectic composition from a single solution. Two distinct phases, Au{sub}5Sn (ζ-phase) and AuSn ((5-phase), were deposited at a composition of 30 at.%Sn. The Au-Sn flip-chip joints were formed at 300 and 400℃ without using any flux. In the case where the samples were reflowed at 300℃, only an (Au,Ni){sub}3Sn{sub}2 IMC layer formed at the interface between the Au-Sn solder and Ni UBM. On the other hand, two IMC layers, (Au,Ni){sub}3Sn{sub}2 and (Au,Ni){sub}3Sn, were found at the interfaces of the samples reflowed at 400℃. As the reflow time increased, the thickness of the (Au,Ni){sub}3Sn{sub}2 and (Au,Ni){sub}3Sn IMC layers formed at the interface increased and the eutectic lamellae in the bulk solder coarsened.
机译:作为目前使用的耗时的焊料预成型件和锡膏的替代品,本研究中使用了共镀金锡锡合金的共电镀方法。使用共电镀工艺,可以从单一溶液将Au-Sn焊料直接镀在共晶成分处或附近的晶片上。以30at。%Sn的成分沉积两个不同的相Au(sub} 5Sn(ζ相)和AuSn((5相)。在300和400℃下形成Au-Sn倒装接头在不使用任何助熔剂的情况下,在300℃下回流样品的情况下,在Au-Sn焊料和Ni UBM之间的界面上仅形成(Au,Ni){sub} 3Sn {sub} 2 IMC层。另一方面,在400℃回流的样品界面上发现了两个IMC层,即(Au,Ni){sub} 3Sn {sub} 2和(Au,Ni){sub} 3Sn。随着回流时间的增加,在界面处形成的(Au,Ni){sub} 3Sn {sub} 2和(Au,Ni){sub} 3Sn IMC层的厚度增加,散装焊料中的共晶薄片变粗。

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