Integrated testing, modeling and failure analysis of CSP~(nl) for board level reliability

摘要

The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones. Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSP~(nl)), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. This paper will focus on the reliability characterization of CSP~(nl) drop test performance, with board design recommendations to eliminate board trace failures which could reduce the component's actual drop test life by five to nine times. The paper demonstrates that CSP~(nl) can exhibit two distinct failure modes under two different test board designs, resulting in a vast difference in drop test lifetimes. Integrated testing, modeling and failure analysis is performed to understand the failure mechanism of both cases.