Minimization of warpage for wafer level package using response surface method

摘要

Warpage issues occurring during semiconductor package process present high probability of loose contacts during assembly processes of chips and package, which has become a critical cause that reduces process yield rates. Therefore, it is necessary to find the right package materials and package structure to minimize such warpage issues. This study performed and investigated the results of a finite-element analysis to find the method to reduce warpage and looked at the effect based on the selection of substrate materials and package structure. Moreover, the study tried to identify factors of, and conditions to minimize, significant effect on warpage by statistically analyzing experimental results based on RSM. According as the substrate and EMC thickness are larger, the warpage is tended to decrease. In addition, the smaller the die-pitch, tends to decrease the warpage. Warpage analysis is performed with respect to the optimal conditions, and it extracts an error of about 0.13 mm as compared with the experimental result. Thus, this analysis result is confirmed that similar to the experimental result.