METHOD FOR FABRICATING WAFER LEVEL CHIP SIZE PACKAGE AND MOLDING APPARATUS USED THEREIN TO PREVENT WAFER WARPAGE USING SIMULTANEOUS MOLDING METHOD

摘要

PURPOSE: A method for fabricating a wafer level chip size package and a molding apparatus are provided to prevent a wafer warpage and a chip crack by molding simultaneously over the upper and lower surfaces of the wafer with the same kinds of sealing material. CONSTITUTION: A wafer including a plurality of semiconductor chips is arranged, on the wafer, conductive bumps are formed. The lower surface of the wafer and the top surface of the wafer on which the conductive bumps are formed are simultaneously molded with a sealing material. The top end of the conductive bumps is exposed by grinding the sealing material formed on the top surface of the wafer. Terminals are formed on the exposed conductive bumps. The wafer that the plurality of semiconductor chips are formed on the top surface thereof is diced one by one.