Adiabatic Computing for CMOS Integrated Circuits with Dual-threshold CMOS and Gate-length Biasing Techniques

摘要

Energy dissipation has become a major consideration concern in portable computers. With sizes of MOS transistors scaling down in nanometer CMOS circuits, the leakage dissipation catches up with the dynamic power consumption gradually and it is becoming an important factor for computer hardware. In present study, an improved effective charge recovery logic (I-ECRL) is proposed. In order to reduce sub-threshold leakage dissipations, adiabatic computing with dual-threshold CMOS (DTCMOS) and gate-length biasing techniques are used for I-ECLR circuits. The I-ECRL flip-flops are also presented. An ISCAS s27 benchmark circuit from the ISCAS85 benchmark set is verified. All circuits are simulated with HSPICE using a NCSU 45 nm process, Results show that both leakage and dynamic dissipations of the I-ECRL circuits with dual-threshold CMOS and gate-length biasing techniques are reduced greatly compared with the conventional CMOS circuits.