1. A process for manufacture of an integrated circuit with MOS transistors, comprising the following operations : a) formation, in an active zone, on a monocrystaline silicon substrate (10) having a first type of conductivity of a thin insulating layer (16) constituting the gate insulator of a field effect transistor, b) deposition and photogravure of a masking resin (18), the pattern of the resin protecting a zone covering the site of the gate to be made and projecting slightly on each side of the latter, c) ionic implantation of impurities having a second type of conductivity opposite to the first to define portions (20 and 22) of regions of source and drain, d) removal of the resin, characterized by the following operations : e) photogravure of the thin insulating layer (16) to uncover the monocrystalline silicon in the zones (36, 38) serving to establish contacts for the source and drain electrodes, f) deposition of a uniform layer of a metallic silicide (40) over the entire substrate, the silicide resting on the insulating thin layer where this is present and coming into direct contact with the monocrystalline silicon in the uncovered zones, g) photogravure of the silicide to define a gate (60), a source electrode (64), a drain electrode (68) and interconnections, h) implantation of ionic impurities to define the ends (72, 74) of the regions of source and drain, auto-aligned with the gate (60), the silicide acting as an implantation mask.
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